The invention relates generally to a semiconductor device. More particularly, the invention relates to a semiconductor device comprising a landing plug and a method for fabricating the same.
Due to increasing degrees of integration of semiconductor devices, intervals between conductive lines, such as gates, have decreased in size. As a result, process margins of forming contacts between the conductive lines have been reduced. In order to secure the process margins of forming contacts, a self-aligned contact (“SAC”) process is performed.
FIGS. 1a and 1b are cross-sectional views illustrating a method for fabricating a semiconductor device according to the prior art. A device isolation structure (not shown) that defines an active region is formed over a semiconductor substrate 10. A portion of the semiconductor substrate 10 is etched by a photolithography process using a mask that defines a recess gate region, to form a recess gate region (not shown) A gate insulating film (not shown) is formed over the active region and in the recess gate region. A recess gate 12, which includes a stacked structure of a gate polysilicon layer 12a, a tungsten layer 12b, and a gate hard mask layer 12c, is formed over the gate insulating film. A gate spacer 14 is formed on a sidewall of the recess gate 12. An interlayer insulating film 16 is formed over the semiconductor substrate 10. A portion of the interlayer insulating film 16 is removed by a self aligned contact (“SAC”) etching process to form a landing plug contact hole (not shown) that exposes the active region. A conductive layer is filled in the landing plug contact hole to form a landing plug 18.
When the recess gate 12 and the recess gate region are misaligned, when a critical dimension (“CD”) of the upper portion in recess gate region is expanded in a subsequent process, or when a CD of the recess gate 12 is reduced, the recess gate region is not covered by the recess gate 12 but is partially exposed (see FIG. 1b). In the SAC etching process, an overlapping margin between the recess gate region and the landing plug 18 results in the generation of an SAC fail (‘A’) between recess gate 12 and landing plug 18.